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256KB AND 512KB SECONDARY CACHE MODULES FOR THE PowerPCTM
Integrated Device Technology, Inc.
IDT7MPV6253 IDT7MPV6255/56
FEATURES
* For CHRP based PowerPCTM systems. * Asynchronous and pipelined burst SRAM options in the same module pinout * Low-cost, low-profile card edge module with 178 leads * Uses Burndy ComputerbusTM connector, part number ELF182KSC-3Z50 * Operates with external PowerPC CPU speeds up to 66MHz * Separate 5V (5%) and 3.3V (+10/-5%) power supplies * Multiple GND pins and decoupling capacitors for maximum noise immunity * Presence Detect output pins allow the system to determine the particular cache configuration.
x 8 asynchronous static RAMs and the IDT7MPV6255/56 use IDT's 71V432 32K x 32 pipelined synchronous burst static RAMs in plastic surface mount packages mounted on a multilayer epoxy laminate (FR-4) board. In addition, each of the modules uses the IDT 71216 16K x 15 Cache-Tag static RAM and IDT FCT logic. Extremely high speeds are achieved using IDT's high-reliability, low cost CMOS technology. The low profile card edge package allows 178 signal leads to be placed on a package 5.06" long, a maximum of 0.250" thick and a maximum of 1.08" tall. The module space savings versus discrete components allows the OEM to design additional functions onto the system or to shrink the size of the motherboard for reduced cost. All inputs and outputs are LVTTL-compatible, and operate from separate 5V (5%) and 3.3V (+10/-5%) power supplies. Multiple GND pins and on-board decoupling capacitors ensure maximum protection from noise.
DESCRIPTION
The IDT7MPV6253/55/56 modules belong to a family of secondary caches intended for use with PowerPC CPUbased systems. The IDT7MPV6253 uses IDT's 71V256 32K
FUNCTIONAL BLOCK DIAGRAM IDT7MPV6253 - 256KB ASYNCHRONOUS VERSION
A14 - A26 ALE ADDRA0 ADDRA1 SRAM OE1 WE#0 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM
8 13
Latch
13
PD0 PD1 PD2 ADDRA0 ADDRA1 SRAM OE0 DH0 - DH7 WE#4 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM 32K x 8 Asynchronous SRAM
8
PD3
DL0 - DL7
WE#1
8
DH8 - DH15
WE#5
8
DL8 - DL15
WE#2
8
DH16 - DH23 WE#6
8
DL16 - DL23
WE#3 STANDBY A14 - A26 TWE# TOE# STANDBY TCLR# TVALID DIRTYIN CLK2
13
8
DH24 - DH31 WE#7 STANDBY
12
8
DL24 - DL31
A2 - A13 TMATCH
8K x 12 Tag Field
8K x 2 Status
DIRTYOUT
drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. PowerPC is a trademark of IBM. Computerbus is trademark of Burndy.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
JUNE 1996
DSC-3608/2
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IDT7MPV6253/55/56 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM IDT7MPV6255 - 256KB PIPELINED BURST VERSION
WE#0 WE#1 WE#2 WE#3 CLK1 CLK0 WE#4 WE#5 WE#6 WE#7 SRAM OE#0 SRAM ADS#0 CNT EN#0 STANDBY BURST MODE A14 - A28
15
32K x 32 Pipelined Burst SRAM
32
DH0-31
32K x 32 Pipelined Burst SRAM
32
DL0-31 PD0 PD1 PD2 PD3
A14 - A26 TWE# TOE# STANDBY TCLR# TVALID DIRTYIN CLK2
13
12
A2 - A13 TMATCH
8K x 12 Tag Field
8K x 2 Status
DIRTYOUT
drw 02
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC3 VCC5 GND VIH VIL Parameter Supply Voltage Supply Voltage Supply Voltage Input High Voltage Min. 3.14 4.75 0 2.2 Typ. 3.3 5.0 0 -- -- Max. 3.6 5.25 0.0 VCC + 0.3 0.8 Unit V V V V V
tbl 01
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Value -0.5 to +4.6 0 to +70 -10 to +85 -55 to +125 50 Unit V C C C mA VTERM Terminal Voltage with Respect for VCC3 to GND TA TBIAS TSTG IOUT Operating Temperature Temperature Under Bias Storage Temperature DC Output Current
Input Low Voltage -0.5(1)
NOTE: 1. VIL = -1.0V for pulse width less than 5ns, once per cycle.
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Power Plane VCC3 VCC5 Ambient Temperature 0C to +70C 0C to +70C GND 0V 0V VCC 3.3V +10/-5% 5.0V 5%
tbl 02
NOTE: tbl 03 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
SRAM ACCESS TIMES
Module Speed 66MHz Asych 15ns Burst(1) 8.5ns Tag 10ns
tbl 04
NOTE: 1. Burst SRAMs are measured by Clock to Data Out (tCD).
2
IDT7MPV6253/55/56 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM IDT7MPV6256 - 512KB PIPELINED BURST VERSION
WE#0 WE#1 WE#2 WE#3 CLK1 WE#4 WE#5 WE#6 WE#7 CLK0 SRAM OE#0 SRAM ADS#0 CNT EN#0 STANDBY BURST MODE A13 - A28
16
32K x 32 Pipelined Burst SRAM
32
WE#0 WE#1 WE#2 WE#3 CLK1 WE#4 WE#5 WE#6 WE#7 CLK0
32K x 32 Pipelined Burst SRAM
32
DH0-31 32K x 32 Pipelined Burst SRAM 32K x 32 Pipelined Burst SRAM
DH0-31
32
32
DL0-31 SRAM OE#1 SRAM ADS#1 CNT EN#1 STANDBY BURST MODE
DL0-31
A13 - A26 TWE# TOE# STANDBY TCLR# TVALID DIRTYIN CLK2
14
12
A1 - A12 TMATCH
16K x 12 Tag Field
16K x 2 Status
PD0 PD1 PD2 PD3
DIRTYOUT
drw 03
CAPACITANCE (IDT7MPV6253 )(1)
(TA = +25C, f = 1.0 MHz)
Symbol Parameter CIN1 Input Capacitance (Address) Input Capacitance CIN2 (ADDR0-1) CIN3 Input Capacitance (OE#) Input Capacitance CIN4 (WE#, TWE#) CI/O I/O Capacitance
(1)
CAPACITANCE (IDT7MPV6255/56 )(1)
(TA = +25C, f = 1.0 MHz)
Max. 15 25 45 8 10 Unit pF pF pF pF pF
tbl 05
Condition VIN = 0V VIN = 0V VIN = 0V VIN = 0V VOUT = 0V
Symbol Parameter(1) CIN1 Input Capacitance (Address) Input Capacitance CIN2 (ADDR0-1) CIN3 Input Capacitance (OE#) Input Capacitance CIN4 (WE#, TWE#) CI/O I/O Capacitance
Condition VIN = 0V VIN = 0V VIN = 0V VIN = 0V VOUT = 0V
Max. 20 -- 15 8 10/20
Unit pF pF pF pF pF
tbl 06
NOTES: 1. These parameters are guaranteed by design but not tested.
NOTES: 1. These parameters are guaranteed by design but not tested.
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IDT7MPV6253/55/56 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION(1)
GND PD1 PD3 DH31 DH29 DH27 DH25 VCC3 SRAM WE3 DH23 DH21 DH18 GND DH16 SRAM WE2 DH14 DH13 VCC5 DH10 DH8 SRAM WE1 DH6 VCC3 DH4 GND CLK0 GND DH1 SRAM WE0 DL31 DL30 GND DL29 DL27 DL25 VCC5 SRAM WE7 DL23 DL21 DL19 GND DL17 SRAM WE6 DL15 DL13 GND DL10 DL8 SRAM WE5 DL6 VCC3 DL5 DL2 GND (1) CLK3 GND (1) CLK4 GND SRAM WE4 (3,4) SRAM ALE VCC3 (3,4) ADDR1 (1) RSVD (2) SRAM CNT EN0 (2,3) SRAM CNT EN1 A27 A24 A22 A20 GND A18 A16 A15 A14 VCC3 A10 A8 A6 GND A4 A2 (2,3) A1 BURST MODE VCC5 TAG VALID TAG WE STANDBY DIRTYOUT GND 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 167 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 GND PD0 PD2 DH30 DH28 DH26 DH24 VCC3 DP3 (1) DH22 DH20 DH19 GND DH17 DP2 (1) DH15 DH12 VCC5 DH11 DH9 DP1 (1) DH7 VCC3 DH5 DH3 DH2 DH0 DP0 (1) GND CLK1 GND DL28 DL26 DL24 DP7 (1) VCC5 DL22 DL20 DL18 DL16 GND DP6 (1) DL14 DL12 DL11 GND DL9 DP5 (1) DL7 DL4 VCC3 DL3 DL1 DL0 GND CLK2 (TAG) GND DP4 (1) SRAM OE0 SRAM OE1 (3) VCC3 ADDR0 (3,4) RSVD (1) SRAM ADS0 (2) SRAM ADS1 (2,3) A28 A26 A25 A23 GND A21 A19 A17 A13 VCC3 A12 A11 A9 GND A7 A5 A3 A0 (1) VCC5 TAG CLR TAG MATCH TAG OE DIRTYIN GND
PIN NAMES
A0 - A28 ADDR0 - ADDR1 CLK0 - CLK4 DH0 - DH31 DL0 - DL31 PD0 - PD3 SRAM ADS0 SRAM ADS1 SRAM ALE SRAM CNT EN1 SRAM OE0 SRAM OE1 SRAM WE0 SRAM WE1 BURST MODE TAG CLR TAG MATCH TAG VALID TAG OE TAG WE DIRTYIN DIRTYOUT STANDBY VCC3 VCC5 GND NC RSVD Burst Mode: 0=Linear, 1=Interleaved Tag Clear Tag Match Tag Valid Tag Output Enable Tag Write Enable Dirty Input Bit Dirty Output Bit Stand By Mode 3.3 Volt Power Supply 5 Volt Power Supply Ground No Connect Reserved
tbl 07
Address Inputs Address Inputs (Asynchronous SRAMs only) Clock Inputs High Order Cache Data Low Order Cache Data Presence Detect Pins SRAM Address Strobe SRAM Address Latch Enable
SRAM CNT EN0 - SRAM Control Enable SRAM Output Enable SRAM Write Enable
PRESENCE DETECT TABLE
PD3 NC NC GND GND PD2 NC GND GND NC PD1 NC NC NC PD0 NC NC NC Module No cache present IDT7MPV6253 IDT7MPV6255 IDT7MPV6256
tbl 08
GND GND
NOTES: 1. These pins are NC (No Connect) on 7MPV6253/55/56. 2. These pins are NC on 7MPV6253. 3. These pins are NC on 7MPV5255. 4. These pins are NC on 7MPV6256.
LOW PROFILE CARD EDGE MODULE TOP VIEW
drw 04
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IDT7MPV6253/55/56 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(VCC5 = 5.0V 5%, VCC3 = 3.3V 10%, TA = 0C to 70C)
Symbol |ILI| |ILI| |ILO| VOL VOH ICC3 ICC5 ISB3 ISB31 Parameter Input Leakage Current (Address) Input Leakage Current (Data and Control) Output Leakage Current Output Low Voltage Output HighVoltage Operating 3.3V Power Supply Current Operating 5V Power Supply Current Standby 3.3V Power Supply Current Full Standby 3.3V Power Supply Current Standby 5V Power Supply Current Test Condition VCC5 = Max, VIN = GND to VCC VCC3 = Max VCC5 = Max, VIN = GND to VCC VCC3 = Max VOUT = 0V to VCC3, VCC3 = Max. IOL = 8mA, VCC3 = Min. IOH= -4mA, VCC3 = Min. VCC3 = Max., STANDBY VIL, f = fMAX, Outputs Open VCC5 = Max., STANDBY VIL, f = fMAX, Outputs Open VCC3 = Max., STANDBY VIH, f = fMAX, Outputs Open VCC3 = Max., STANDBY VCC3 - 0.2V, f = 0, VIN 0.2V or VIN VCC3 - 0.2V, Outputs Open VCC5 = Max., STANDBY VIH f = fMAX, Outputs Open Min. -- -- -- -- 2.4 -- -- -- -- '53 Max. 20 10 10 0.4 -- 1000 290 100 30 '55 Max. 30 10 10 0.4 -- 500 290 100 30 '56 Max. 50 20 20 0.4 -- 590 290 190 50 Unit A A A V V mA mA mA mA
ISB5
--
30
30
30
mA
tbl 09
AC TEST CONDITIONS - 3.3V POWER SUPPLY
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
tbl 10
+3.3V 320 DATAOUT 350 30pF* DATAOUT 350
+3.3V 320
5pF*
*including scope and jig capacitances Figure 1. Output Load
drw 05
*including scope and jig capacitances Figure 2. Output Load (for tOHZ, tCHZ, tOLZ and tCLZ)
drw 06
5
IDT7MPV6253/55/56 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS - IDT7MPV6253
FRONT VIEW 5.050 5.070 SIDE VIEW 0.225 MAX
1.060 1.080
PIN 90 2.150 2.170
0.072 0.076 1.240 1.260
0.075 0.081 4 X 0.200 1.250 1.270 0.055 0.069
2 X 0.195
N/A
0.050 TYP BACK VIEW
PIN 1
drw 07
IDT7MPV6255
FRONT VIEW 5.050 5.070 SIDE VIEW 0.200 MAX
1.060 1.080
PIN 90 2.150 2.170
0.072 0.076 1.240 1.260
0.075 0.081 4 X 0.200 1.250 1.270 0.055 0.069
2 X 0.195
N/A
0.050 TYP BACK VIEW
PIN 1
drw 08
6
IDT7MPV6253/55/56 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS - IDT7MPV6256
FRONT VIEW 5.050 5.070 SIDE VIEW 0.250 MAX
1.060 1.080
PIN 90 2.150 2.170
0.072 0.076 1.240 1.260
0.075 0.081 4 X 0.200 1.250 1.270 0.055 0.069
2 X 0.195
0.050 TYP BACK VIEW
PIN 1
drw 09
ORDERING INFORMATION
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank Commercial (0C to +70C)
M
178 lead Module, Card Edge Low Profile (CELP)
15 66
Speed in Nanoseconds (Asynchronous) Speed in Megahertz (Pipelined Burst)
S
Standard Power
7MPV6253 256KB Asynchronous Cache Module 7MPV6255 256KB Pipelined Burst Cache Module 7MPV6256 512KB Pipelined Burst Cache Module
drw 10
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